Transition from system anaylsis to logical architecture after system-to-subsystem transformation

If i am realizing capabilities from the system analysis to the logical architecture, and then validated the system analysis i get this warning.

So I thought it is related that maybe there is no realization link between the respective capability in the system analysis and the capability realization in the logical architecture.

But acutally it is realized with a link. So could anyone help me to fix this please?

Hi @m.naderhirn,

please see How to get rid of validation warnings from rules TJ_LA_02 (capability refinement) and TC_DC_11 (logical component realization) and Question on validation rule TJ_G_04.

The first link deals with the very same issue you are seeing (validation message from TJ_LA_02). My conclusion from these two threads is that the built-in validation of Capella is a great concept and a lot of the validation checks are already really helpful. However, it seems like a more serious use of the validation feature requires the definition of your own validation checks as described here:

As of now, I’m living with the messages from my model that I cannot fix. I’m not happy with this but I currently don’t have the time to write my own validation checks since I’m still in the process of evaluating the tool. I really like Capella and would be excited if the validation feature were to get some attention in a future release of Capella. If anyone started a concerted effort to improve the feature, I’d try to join in for fixing the issues I’m seeing.

Best regards,

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