Logical architecture

Hi all,
I would like some details about how this rule runs:
I starting logical architecture in my model. The reason for dividing my system is activation level (modes)
Several function were divided, and the system too. The logical components allocate (together) all leaf LF.
But still I ave the mention at warning level that the parent functions realizing the SF are not allocated.
Only leaf LF shall be allocated by leaf LC (which is my understanding) then these warning are noise, while the rule DWF_DC_15 about only allocating leaf functions is activated.
NB: some of my SF were just transitioned LF without split because they could be allocated as is by one of my LCs